The present invention relates to a design technique of a semiconductor circuit; and, more particularly, to a synchronous semiconductor memory device including a clock synchronization circuit and a clock tree on/off control circuit of the clock synchronization circuit.
Generally, in systems or circuits, a clock is a reference signal for synchronizing execution timing and it is also used for more high-speed execution without any error. The clock skew is occurred in an internal circuit when the clock inputted from an external circuit is used in the internal circuit. There are used a phase locked loop (PLL), a delay locked loop (DLL), and so on for compensating the clock skew and thereby equalizing the internal clock with the external clock.
On other hand, the PLL is commonly used in various circuits; however, the DLL is generally used in a double data rate synchronous dynamic random access memory (DDR SDRAM) and a synchronous semiconductor memory device because the DLL has more advantage of noise compared to the PLL.
In a typical semiconductor memory device, e.g., the DRAM, it is issued how to reduce current consumption in proportion with increase of an operating frequency for high-speed execution. Meanwhile, the DRAM is recently used not only in a main memory device of the computer system but also in portable appliances. Therefore, the reduction of current consumption is one of critical request for DRAM design.
A method used in PLL, DLL, and so on is used for outputting data being correspondent to the external clock. Clock synchronous circuits are used in the synchronous semiconductor memory device for a better capability of transmitting data. The clock outputted from the clock synchronous circuit is used in passing the outputted data. If using the clock outputted from the clock synchronous circuit, data-load is not an overburden in a normal execution of the synchronous semiconductor memory device; however, it is critical problem in a stand-by mode. The reason for this result is that an available current is larger in the normal execution than that in the stand-by mode.
Thus, there have been many progressed researches for reducing the current consumption in the stand-by mode of the synchronous semiconductor memory device. In the stand-by mode, the current consumption is changed in response to the operating frequency. The higher the operating frequency is, the more the current consumption is occurred.
FIG. 1 is a timing diagram showing an execution timing of a conventional DDR SDRAM.
As shown, a row activating instruction ACT, a read instruction RD and a row inactivating instruction PCT are supplied for outputting data in the DDR SDRAM. A DLL clock has toggled for sections from a moment of supplying the row activating ACT to a moment of outputting the last data. Thus, a DLL clock tree is turned on in the sections except for a section that the clock enable signal CKE is in logical low xe2x80x98Lxe2x80x99.
In FIG. 1, there is presented case that an additive latency AL is xe2x80x980xe2x80x99, a CAS latency CL is xe2x80x983xe2x80x99, and a burst length is xe2x80x988xe2x80x99. For reference, the use of the additive latency AL is technique used in DDR II and the AL is an index defining how many clocks are needed for perceiving the instruction in read or write timing like the CAS latency.
Typically, the section that the clock enable signal CKE is in logical low xe2x80x98Lxe2x80x99 is called a power-down state, and a section that the clock enable signal CKE is in logical high xe2x80x98Hxe2x80x99 is called a non power-down state. The stand-by mode is not only the non power-down state but also a state that the DDR SDRAM does not operate.
However, there is a problem that unnecessary current consumption is occurred in the synchronous memory device because the DLL clock is continuously toggled during the stand-by mode. This problem is also occurred in the synchronous memory device using PLL.
It is, therefore, an object of the present invention to provide a semiconductor memory device for reducing power consumption by turning off a DLL clock tree in stand-by mode.
In addition, it is an object of the present invention to provide a clock tree on/off control logic using a method for effectively controlling a clock tree of the clock synchronization circuit by using signals related to a row address strobe.
In accordance with an aspect of the present invention, there is provided a synchronous semiconductor memory device includes a clock synchronization means for synchronizing a data output with a external clock; and a clock tree on/off control means for delaying an enable timing of a RAS idle signal for a predetermined time after a row inactive instruction is supplied, turning on/off a clock tree of the clock synchronization means in response to the RAS idle signal.
In accordance with another aspect of the present invention, there is provided a clock tree on/off control means of a clock synchronous circuit for controlling turning the clock tree of the clock synchronous circuit on/off including a first edge triggered pulse generating means for generating a first edge triggered pulse by receiving a RAS idle signal; a clock buffering means for buffering a clock signal having the same period with an external clock in response to the RAS idle signal and a feedback clock tree control signal; a clock period configuration means for deciding a period as same as a clock period of a predetermined output signal of the clock buffering means in response to the RAS idle signal; a second edge triggered pulse generating means for generating a second edge triggered pulse by receiving an output signal of the clock period configuration means; and a latching means for receiving both output signals of the first edged triggered generating means as a set signal and the second edged triggered generating means as a reset signal.